آی سی درایور TC358762XBG

Display drivers are devices that provide the interface between a microprocessor (MPU) or microcontroller (MCU) and a display based upon a particular technology.

This Functional Specification defines operation of a de-serializer chip, TC358762XBG. The serial data stream is supplied by the baseband processor via the DSI 1.01 interface. TC358762XBG chip de-serializes the stream into a parallel one. The parallel output bus can be either a DPI or a DBI bus. The usage of either DPI or DBI bus is mutually exclusive. The DSI host controls/configures TC358762XBG chip via DSI's Generic Long Write packets. The host controls (commands) the peripheral display device by sending DSI packets to TC358762XBG. TC358762XBG routes the commands either through DBI host, SPI master or DBI-C host interface, I/F, block to the peripheral device. TC358762XBG supports both DCS and generic commands. The commands output through these interfaces are intended for the peripheral display device to interpret and execute; TC358762XBG does not interpret them, except a few DCS commands mentioned explicitly in this document.

TC358762XBG supports bi-directional DSI link. The host reads TC358762XBG's registers via DSI's Generic Read (2 parameter) packets. Host can also access the status registers of peripheral display device attached to TC358762XBG by issuing read commands.

 ² MIPI D-PHY: 1.2V

² I/O: 1.8V – 3.3V (all IO pins must be same power level)

² Core: 1.2V TC358762XBG 13 / 22 2017-09-25

PLL OFF mode - Sleep mode (DSI-CLK stops toggle) Ø

IOs: 0.05 µW Ø CORE: 23 µW Ø D-PHYs: 3 mW Ø PLLs: Off (PLL power – 0V)

² BGA 64 pins

² 5.0mm × 5.0mm × 1mm

² 0.5mm ball pitch

● Standard followed: ² MIPI DSI version 1.01, Feb 2008 ² MIPI D-PHY version 0.9, Oct 2007 ² MIPI DPI version 2.0, Sep, 2005 ² MIPI DBI-2 version 2.00, Nov 2005 ² MIPI DCS Command version 1.02, Dec 2008 ● DSI Receiver ² Dual Data Lane DSI Link with Bi-direction support at Data Lane 0 ² Maximum speed at 800 Mbps/lane ² Video input data formats: RGB-565, RGB-666 and RGB-888 ² Video input frame rates: Up to 60 fps for WXGA (1366 × 768) ² Support various DSI packet types ² Provide the path for DSI host/transmitter to control TC358762XBG and its attached Display Device

● DPI Host ² Bus speed up to 75 MHz burst rate with data rate up to 216 Mbytes/s ² Support the following pixel formats: - RGB666 18 bit per pixel - RGB666 loosely packed 18 bit per pixel - RGB565 16 bit per pixel - RGB565 loosely packed 16 bit per pixel - RGB888 24 bit per pixel Ø With the Toshiba Magic Square algorithm, an RGB666 18-bit or 16-bit LCD panel can produce a display equivalent to that of an RGB888 24-bit LCD panel with up to 16- million colors Ø Programmable output polarity Ø Support up to frame size 1366 × 768 at 60 fps

● DBI Host ² Read/Write Data/Command from the external DBI slave device ² Support DCS commands, which is compliant with MIPI DBI-B standard ² Support Intel 80xx CPU I/F with either 8-bit or 16-bit commands ² Programmable Output Data Format and Bus Width - 8 bit Bus, RGB 565 (2 cycles/pixel) - 8 bit Bus, RGB 666 (3 cycles/pixel) - 8 bit Bus, RGB 888 (3 cycles/pixel) - 9 bit Bus, RGB 666 (2 cycles/pixel) - 16 bit Bus, RGB 565 (1 cycles/pixel) - 16 bit Bus, RGB 666 (3 cycles/2 pixel) note1 - 16 bit Bus, RGB 888 (3 cycles/2 pixel) note1 - 18 bit Bus, RGB 666 (1 cycles/pixel) - 24 bit Bus, RGB 888 (1 cycles/pixel) Ø Support up to 864×480 at 60 fps (or 1280×720 at 30 fps)